Direct memory access, or DMA, is a method for direct communication from a peripheral device to memory with no programming involved. The data is moved to memory via the bus without program intervention. The only effect on the executing program is some slowing down of execution time because the DMA activity “steals” bus cycles that would otherwise be used to access memory for program execution.
DMA is a prime example of a hardware function in the chip that benefits from queued commands. There are two main aspects to this: (1) there are multiple DMA operations that need to be performed in one macroblock (MB) time interval, and (2) there are performance advantages in giving the DMA two macroblock times to complete each macroblock set of DMA operations, i.e., longer latency deadlines can help to tolerate DRAM latency. Because the DMA engine receives multiple commands in a given macroblock time interval, some form of command list is necessary for acceptable performance. There are up to (approximately) twelve DMA operations per macroblock for prediction fetches, and up to (approximately) four DMA operations per macroblock for write-backs, leading to a need for at least 16 DMA operations per macroblock. With the pipeline structured to allow two macroblock times of latency for each one macroblock set of operations, the complete list of commands is not expected to be empty at any time during normal operation. For example, commands for a first macroblock are sent to the DMA engine. Then commands for a second macroblock are sent to the DMA engine, while DMA operations for the first macroblock need not be complete yet. The first macroblock operations should be done prior to the time when the DMA commands for a third macroblock are sent to the DMA engine, while the second macroblock operations need not be done by that time. This means that it is not possible for firmware (or anything else) to determine that the DMA engine is “done” with a particular macroblock by checking to see if the entire command queue (assuming there is one) has been completed.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.